In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques in such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become more difficult.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, thin film electrodeposition techniques require a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique. For instance, a conventional thin film electrodeposition process for depositing solder bumps is shown in FIGS. 1A.about.1F.
A conventional semiconductor structure 10 is shown in FIG. 1A. The semiconductor structure 10 is built on a silicon substrate 12 with active devices built therein. A bond pad 14 is formed on a top surface 16 of the substrate 12 for making electrical connections to the outside circuits. The bond pad 14 is normally formed of a conductive metal such as aluminum. The bond pad 14 is passivated by a final passivation layer 20 with a window 22 opened by a photolithography process to allow electrical connection to be made to the bond pad 14. The passivation layer 20 may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer 20 is applied on top of the semiconductor device 10 to provide both planarization and physical protection of the circuits formed on the device 10.
Onto the top surface 24 of the passivation layer 20 and the exposed top surface 18 of the bond pad 14, is then deposited an under bump metallurgy layer 26. This is shown in FIG. 1B. The under bump metallurgy (UBM) layer 26 normally consists of an adhesion/diffusion barrier layer 30 and a wetting layer 28. The adhesion/diffusion barrier layer 30 may be formed of Ti, TiN or other metal such as Cr. The wetting layer 28 is normally formed of a Cu layer or a Ni layer. The UBM layer 26 improves bonding between a solder ball to be formed and the top surface 18 of the bond pad 14.
In the next step of the process, as shown in FIG. 1C, a photoresist layer 34 is deposited on top of the UBM layer 26 and then patterned to define a window opening 38 for the solder ball to be subsequently formed. In the following electrodeposition process, a solder ball 40 is electrodeposited into the window opening 38 forming a structure protruded from the top surface 42 of the photoresist layer 34. The use of the photoresist layer 34 must be carefully controlled such that its thickness is in the range between about 30 .mu.m and about 40 .mu.m, preferably at a thickness of about 35 .mu.m. The reason for the tight control on the thickness of the photoresist layer 34 is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used to achieve a high imaging resolution. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process. To maintain a reasonable accuracy in the imaging process on the photoresist layer 34, a reasonably thin photoresist layer 34 must be used which results in a mushroom configuration of the solder bump 40 deposited therein. The mushroom configuration of the solder bump 40 contributes greatly to the inability of a conventional process in producing fine-pitched solder bumps.
Referring now to FIG. 1E, wherein the conventional semiconductor structure 10 is shown with the photoresist layer 34 removed in a wet stripping process. The mushroom-shaped solder bump 40 remains while the under bump metallurgy layer 26 is also intact. In the next step of the process, as shown in FIG. 1F, the UBM layer 26 is etched away by using the solder bump 40 as a mask in an wet etching process. The solder bump 40 is then heated in a reflow process to form solder ball 42. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
In recent years, chip scale packages (CSP) have been developed as a new low cost packaging technique for high volume production of IC chips. One of such chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide larger number of input/output terminals than that possible from a conventional quad flat package, even though a typical quad flat package is better protected mechanically from the environment.
A unique feature of the chip scale package is the use of an interposer layer that is formed of a flexible, compliant material. The interposer layer provides the capability of absorbing mechanical stresses during the package forming steps and furthermore, allows thermal expansion mismatch between the die and the substrate. The interposer layer, therefore, acts both as a stress buffer and as a thermal expansion buffer. Another unique feature of the chip scale package, i.e. such as a micro-BGA package, is its ability to be assembled to a circuit board by using conventional surface mount technology (SMT) processes.
The conventional flip chip bonding process requires multiple preparation steps for IC chips, i.e. the formation of aluminum bond pads on the chip, the under-bump-metallurgy process on the bond pads, the deposition of solder bumps and the reflow of the solder balls. When flip chip bumping is performed on a wafer scale and that the formation of the solder bumps or solder balls is out of specification, the whole wafer is frequently scrapped since there are no reliable methods for reworking the wafer. This can be very costly considering the cumulative costs for fabricating the multiplicity of IC devices on the wafer. The major difficulty in reworking the wafers has been the removal of solder bumps or solder balls that are on the wafer surface so that the bumping process can be repeated to produce bumps within specification.
It is therefore an object of the present invention to provide a method for reworking a bumped semiconductor wafer without scrapping the wafer when solder bumps or solder balls formed on the wafer are out of specification.
It is another object of the present invention to provide a method for reworking a bumped semiconductor wafer by removing the solder bumps or solder balls from the wafer surface such that a solder bumping process can be repeated on the wafer.
It is a further object of the present invention to provide a method for removing a multiplicity of solder bodies (of either solder bumps or solder balls) from an active surface of a semiconductor wafer by exposing the surface to an etchant that has a high etch rate for a copper seed layer placed under the solder bodies and a low etch rate for an aluminum bond pad or an organic passivation layer insulating the bond pad.
It is another further object of the present invention to provide a method for removing a multiplicity of solder bodies connected to a semiconductor wafer through a copper wetting layer from the wafer by dissolving the copper wetting layer by an etchant.
It is still another object of the present invention to provide a method for removing a multiplicity of solder bodies connected to a semiconductor wafer by a copper wetting layer from the wafer by exposing the copper wetting layer to an etchant that contains Ce (NH.sub.4).sub.2 (NO.sub.3).sub.6.
It is yet another object of the present invention to provide a method for removing a multiplicity of solder bodies connected to a semiconductor wafer through a copper wetting layer from the wafer by exposing the copper wetting layer to an etchant containing between about 3 wt. % and about 30 wt. % of Ce (NH.sub.4).sub.2 (NO.sub.3).sub.6.
It is still another further object of the present invention to provide a method for removing a multiplicity of solder bumps connected to a semiconductor wafer through a copper wetting layer from the wafer surface by exposing the copper wetting layer to an etchant containing Ce (NH.sub.4).sub.2 (NO.sub.3).sub.6 and ultrasonic vibration to etch away the copper wetting layer.
It is yet another further object of the present invention to provide a method for removing a multiplicity of solder balls connected to a semiconductor wafer through a copper wetting layer from the wafer surface by exposing the multiplicity of copper wetting layer to an etchant that has an etch rate toward copper at least 5 times the etch rate toward aluminum.